Agilent/Keysight M8040A

The Keysight M8040A is a high-performance Bit Error Rate Tester (BERT) for physical layer characterization and compliance testing of high-speed digital interfaces up to 64 GBaud. It supports NRZ, PAM3, and PAM4 signaling formats, enabling validation of emerging standards including 400 GbE, OIF CEI-112G, PCIe 6.0, and USB4. The instrument delivers true real-time PAM4 error detection for low BER measurement and receiver margin optimization.

– Technical Specifications

Signal Generation
• Data rates: 2 to 64 GBaud (NRZ, PAM3, PAM4)
• Amplitude: 0.9 Vpp @ 58 GBd
• De-emphasis: 5-tap de-emphasis with multiple presets for loss compensation
• Jitter injection: Random Jitter (RJ), Periodic Jitter (PJ1, PJ2), Sinusoidal Jitter (SJ), Baudrate Jitter (BUJ), Clock/2 Jitter, Spread Spectrum Clocking (SSC, rSSC), Spectrally Distributed RJ (sRJ), LF-PJ, multi-tone PJ
• Pattern generation: Algorithmic PRBS, QPRBS (OIF-CEI variants), memory-based patterns, pattern sequencer with loops, user-defined patterns, deterministic sequences
• FEC encoding and error insertion supporting IEEE 802.3cd with Sync to A400
• PCIe pre-coder support
• Interference injection: Random Interference (RI), Sinusoidal Interference (SI)

Signal Analysis
• PAM4 error detection in real-time up to 58 GBaud
• Clock data recovery (CDR) with adjustable loop bandwidth to 16 MHz max
• Feed-Forward Equalization (FFE) for eye diagram re-opening
• True error analysis for low BER and SER measurements
• Error distribution analysis for burst error debugging
• Link training support: PCIe (8/16/32/64 GT/s), USB 3.2, USB4, Thunderbolt 3/4, SATA, SAS, CCIX

– Key Features

• Integrated remote head design with 1.85 mm cables minimizes signal degradation
• Supports both internal and external clock recovery control (N1076A/B, N1077A, N1078A)
• Part of the Keysight M8000 series for scalable, integrated test solutions

– Typical Applications

• High-speed serial interface validation (PCIe 6.0, USB4, 400 GbE)
• Receiver performance characterization
• Device margin optimization
• Standards compliance testing

– Compatibility & Integration

Scalable within the M8000 series architecture; supports external clock recovery units for flexible system integration.