Anritsu MP1763C 12.5GHz Pulse Pattern Generator

The Anritsu MP1763C is a high-performance Pulse Pattern Generator designed for the research and development of high-speed logic, ICs, and digital systems. It is capable of generating pulse patterns up to 12.5 GHz and is well-suited for testing high-speed digital communication systems and devices, including those in telecommunications and SAN markets. When used in conjunction with the Anritsu MP1764C or MP1764D Error Detector, it forms a Bit Error Rate Test Set (BERTS) that supports evaluation from R&D through manufacturing and production at speeds ranging from 50 Mbit/s to 12.5 Gbit/s. The MP1763C is recognized for its high-quality waveform, comprehensive frequency coverage, and advanced pattern generation capabilities, making it a valuable tool for rigorous testing and analysis.

### Technical Specifications

**Core Performance:**
* **Frequency Range:** 0.05 GHz to 12.5 GHz
* **Data Patterns:** Generates four types of pulse patterns: alternate, programmable, zero substitution, and pseudorandom.
* **Pseudorandom Patterns:** Includes seven 2^N-1 (N=7, 9, 11, 15, 20, 23, 31) pseudorandom patterns. The mark ratio for pseudorandom patterns can be selected from among 0/8, 1/8, 1/4, 1/2, 3/4, 7/8, and 8/8.
* **Programmable Pattern Length:** Capable of generating programmable data patterns up to 8 M bits. This allows for the generation of six frames of STM-64/STS-192.
* **Waveform Quality:** Produces a high-quality eye diagram with fast rise/fall times (less than 30 ps), low distortion (less than 10%), and low jitter (less than 20 ps p-p crossover jitter). A high Q factor (greater than 40 dB) is achievable.
* **Output Quality:** Waveform distortion is ≤15% or ≤150 mV, whichever is greater.

**Clock Generation (Option 01):**
* **Internal Clock Frequency Range:** 0.05 GHz to 12.5 GHz
* **SSB Phase Noise:**
* ≤–85 dBc/Hz (0.05 to 4 GHz) at 10 kHz offset, 1 Hz bandwidth
* ≤–80 dBc/Hz (4 to 8 GHz) at 10 kHz offset, 1 Hz bandwidth
* ≤–75 dBc/Hz (8 to 10 GHz) at 10 kHz offset, 1 Hz bandwidth
* ≤–70 dBc/Hz (10 to 12.5 GHz) at 10 kHz offset, 1 Hz bandwidth
* **Clock Delay:** Variable delay function for clock signals, adjustable by ±500 ps in 1 ps steps. This enables measurement of time-dependent characteristics or phase margins.
* **Low FM/PM-Noise Clock Generator:** Features a low FM/PM-noise clock generator.

**Output Characteristics:**
* **Data Output Channels:** Two data output channels (DATA and DATA).
* **Clock Output Channels:** Three clock output channels (CLOCK1, CLOCK1, CLOCK2).
* **Parallel Output:** Standard 1/8 parallel output. Options for 1/4 parallel output (MP1763C-03) and 1/4 differential output (MP1763C-08) are available. The 1/4 differential output is noted as an industry-first for a 12.5G BERT system, specifically for SAN market device applications.
* **Differential Inputs:** Supports differential inputs, essential for applications like XAUI, SFI-4P2 4-Lane devices, and PCI Express.
* **Complementary Outputs:** Provides complementary outputs for both data and clock signals.
* **Amplitude:** Data output amplitude is adjustable from 0.25 Vp-p to 2.0 Vp-p.
* **Offset:** DC offset is selectable, adjustable within ±2 V. This allows for measurement of amplitude and offset margins.
* **Pulsing Capability:** The MP1763C can be externally gated using the GATING INPUT (0/-1 Volt Logic, 0V = Data On, -1V = Data Off) for burst signal generation.

**Interfaces and Control:**
* **GPIB Interface:** Conforms to IEEE 488.2 standard for automatic or remote measurement via an external controller.
* **Floppy Disk Drive:** Built-in 3.5-inch floppy disk drive for storing preset data and enabling rapid measurements.
* **Memory Cards:** Utilizes memory cards for storing data and programs, with a caution regarding handling to prevent data loss.

**Compatibility and Applications:**
* **Applications:** Ideal for research and development of high-speed logic, ICs, digital systems, high-speed digital communication systems, telecommunication systems (STM-0/STS-1 to STM-64/STS-192), 10 GbE, OUT-2, and 4.25G Fibre Channel systems. Also suitable for SAN market device applications and optical submarine transmission systems.
* **Companion Instruments:** Used in combination with the Anritsu MP1764A, MP1764C, or MP1764D Error Detector for Bit Error Rate (BER) testing.

### Physical and Electrical

* **Power Consumption:** ≤300 VA
* **Output Levels:** Both 50 Ω GND and ECL outputs are supported.

### Standards Compliance

* **EMC:** Conforms to EN 61326: 1997 + A1: 1998 + A2: 2001 + A3: 2003 (Class A), EN 61000-3-2: 1995/A2: 1998 (Class A).
* **LVD:** Conforms to Council Directive 73/23/EEC.
* **Other Directives:** Council Directive 89/336/EEC.

### Operational Notes

* **Burst Mode:** Features like AUTO SEARCH, EYE MARGIN, and ERROR ANALYSIS do not function in Burst Mode. BLOCK WINDOW and BIT WINDOW operate in Burst Mode. Burst Switch “ON” disables Sync Loss and Clock Loss alarms.
* **Synchronization:** The MP1764C Error Detector has fast synchronization times for both standard PRBS and user-defined patterns.
* **Loop Testing:** The MP1763C and MP1764C are well-suited for circulating loop measurements, which simulate long-haul fiber transmission systems.

Why Choose Aumictech for Anritsu MP1763C?
At Aumictech, we specialize in supplying high-end pulse pattern generator equipment. Whether you need to test high-speed digital communication systems, develop advanced ICs, or ensure the integrity of complex logic circuits, our team ensures the Anritsu MP1763C delivers maximum performance for your application.