Fluke / Wavetek 1391 50 MHz Pulse Generator

The Fluke/Wavetek 1391 is a 50 MHz VXIbus programmable pulse generator delivering versatile signal generation across continuous, triggered, gated, and burst operating modes. Single, double, and delayed pulse configurations are supported, with square wave output extending to 100 MHz at 50% duty cycle. All pulse parameters—period, width, and delay—are programmable to 4-digit resolution. The instrument integrates into any manufacturer’s VXI chassis via SCPI or MATE/CIIL command sets, making it ideal for automated test systems requiring precise pulse timing and amplitude control.

## Technical Specifications

• **Frequency Range:** 1 mHz to 50 MHz (pulse mode); up to 100 MHz (square wave)
• **Pulse Width:** Programmable up to 2000 seconds
• **Pulse Delay:** Programmable up to 2000 seconds
• **Rise/Fall Transition Times:** Settable from 5 ns to 50 ps
• **Output Amplitude:** ±8 V into 50 Ω termination; peak-to-peak continuously variable from 150 mVp-p to 16 Vp-p in 10 mV steps across a programmable +16 V window
• **Programmable Resolution:** 4-digit resolution for period, width, and delay parameters
• **Form Factor:** Single-slot, C-size VXI module

## Key Features

• Pulse Amplitude Modulation (PAM) support via external signal input for upper, lower, or both amplitude levels
• Four operating modes: continuous, triggered, gated, and burst pulse generation
• VXIbus SUMBUS capability for series operation and master clock/trigger bus slaving for parallel multichannel configurations
• Self-adjustment utilities with non-volatile calibration memory
• SCPI Version 1.0 (April 1990) and Version 1992.0 compliance; MATE/CIIL language support

## Interfaces

• VXIbus (C-size module)
• PAM IN (external modulation)
• TRIG IN (external trigger)
• SYNC OUT (synchronization output)
• PULSE OUT (BNC connector)

## Compatibility & Integration

Operates within any VXI chassis using standard SCPI or MATE/CIIL protocol. VXIbus SUMBUS support enables series multichannel operation; independent slaving to external master clock/trigger sources supports parallel configurations in complex test environments.