NI SCC-ACC01 Accelerometer Input Module

The NI SCC-ACC01 Accelerometer Input Module delivers single-channel signal conditioning for dynamic accelerometer measurements on NI SCC carrier boards. It accepts accelerometer signals, applies fixed 2× gain amplification, and filters the output through a 0.8 Hz high-pass filter and 19 kHz low-pass Bessel filter for clean, conditioned data delivery to E Series DAQ devices. The module integrates a 4 mA current source for accelerometer excitation and operates across industrial vibration monitoring, modal analysis, and structural testing environments.

– Technical Specifications

• Input Channels: 1 differential
• Input Range: ±5 V
• Gain: Fixed 2×
• High-Pass Filter: 0.8 Hz
• Low-Pass Filter: 19 kHz Bessel
• Accelerometer Excitation: 4 mA current source
• Input Impedance: 0.39 µF in series with 5 MΩ
• Channel-to-Channel Input: 42 VDC
• Analog Power Consumption: 89 mW maximum
• Digital Power Consumption: 420 mW maximum
• Dimensions: 8.89 cm × 2.92 cm × 1.85 cm
• Operating Temperature: 0 °C to 50 °C
• Storage Temperature: -20 °C to 70 °C
• Relative Humidity: 10% to 70%

– Key Features

• Built-in signal conditioning with cascaded filtering eliminates noise and DC bias from raw accelerometer signals
• High-impedance bias resistors accommodate floating and ground-referenced signal sources without external components
• Flexible carrier board socket configuration supports single-stage direct connection or dual-stage cascading with second-stage modules
• Ground connection option on SC-2345 screw-terminal block reduces noise in high-interference environments

– Typical Applications

• Machinery health monitoring and predictive maintenance
• Modal analysis and transfer function measurement
• Structural health assessment and vibration characterization

– Compatibility & Integration

• Carrier Boards: SC-2345, SC-2350
• DAQ Interface: E Series DAQ devices via socket-selected channel routing
• Power Requirements: SCC-PWR01, SCC-PWR02, or PS01 power supply
• Socket Configuration: Single-stage on J(X+1); dual-stage on J(X+9) with second module on J(X+1), where X = 0 to 7