Synthesys Research CR12500A

The Synthesys Research CR12500A is an instrumentation-grade clock recovery instrument for high-speed digital communication testing. It delivers accurate jitter analysis, signal integrity measurements, and compliance validation across data rates from 150 Mb/s to 12.5 Gb/s, with optional extension to 14.3 Gb/s. Operating standalone or integrated with external test systems, the CR12500A combines precise clock recovery with direct spectral jitter decomposition and physical layer analysis capabilities.

– Technical Specifications

Data Rate Coverage
• 150 Mb/s to 12.5 Gb/s continuous operation
• Optional 14.3 Gb/s capability (Option 143)
• BER measurements supported down to 100 Mb/s
• Internal or external clock operation

Clock Recovery
• Variable loop bandwidth: 100 kHz to 12 MHz
• Programmable peaking with first and second-order rolloff
• Auto-lock capability with LED indication
• Self-measured PLL frequency response display

Jitter Analysis
• Full jitter decomposition: DJ, DDJ, ISI, DCD, BUJ, RJ
• Jitter Triangulation methodology for long patterns (PRBS-23, PRBS-31)
• Direct Duty Cycle Dependent Jitter (DCD) measurement
• Jitter spectrum frequency range: 200 Hz to 90 MHz at 100 Hz resolution
• User-settable frequency-gated band-limited integrated jitter
• Preset band limits for PCIe 2.0 compliance
• Spectrum analyzer display with cursor measurements

Signal Conditioning & I/O
• Single-ended and differential 50 Ω inputs and outputs
• DC-coupled data path
• Full and divided clock outputs with selectable divide ratios
• Differential divided clock outputs for instrument-grade test clocks
• External clock input with stress imposition capability
• Spread Spectrum Clock (SSC) analysis support

Physical Layer Measurements
• Eye diagrams and mask measurements with variable depth
• Clock phase deviation measurement (frequency and time domain)
• Edge density and mark density determination
• SSC signal analysis with large frequency excursion tolerance

– Typical Applications

Serial data compliance testing, PLL characterization, jitter source isolation, spread spectrum clock validation, physical layer signal integrity assessment.

– Compatibility & Integration

Operates with 50 Ω test infrastructure. Accepts internal or external reference clocks. Compatible with long-pattern PRBS test sequences.